Field
Embodiments relate to processors. In particular, embodiments relate to processors having instruction sets that include instructions that use control indexes.
Background Information
Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements or multiple pairs of data elements simultaneously or in parallel. The processor may have parallel execution hardware responsive to the packed data instruction to perform the multiple operations simultaneously or in parallel.
Multiple data elements may be packed within one register or memory location as packed data or vector data. In packed data, the bits of the register or other storage location may be logically divided into a sequence of multiple data elements. For example, a 256-bit wide packed data register may have four 64-bit wide packed data elements, eight 32-bit wide packed data elements, sixteen 16-bit wide packed data elements, etc. Each of the packed data elements may represent a separate individual piece of data (e.g., a red, green, blue, or alpha color component of a pixel, or a real or imaginary component of a complex number, etc.) that may be operated upon separately or independently of the others.
Some SIMD architectures have instructions to flexibly rearrange packed data elements within one or more source packed data according to control indexes. Examples of such instructions are permute instructions and shuffle instructions. The control indexes control how the packed data elements are rearranged by the instructions.